1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a stacked memory cell for use in a high-density complementary metal oxide semiconductor (CMOS) static random access memory (SRAM).
This application claims the benefit of Korean Patent Application No. 2005-0129470, filed Dec. 26, 2005, the disclosure of which is hereby incorporated herein by reference in its entirety.
2. Discussion of Related Art
In general, in order to meet the ever-increasing requirements for high performance electronic systems, semiconductor memory devices, such as SRAMs, need to constantly increase in speed and density. Hence, the makers of the semiconductor memory devices have exerted large efforts to incorporate ever-smaller memory cells in various integrated circuits.
FIG. 1 is an equivalent circuit diagram of a known six-transistor (6T) CMOS SRAM cell. As shown in FIG. 1, the 6T CMOS SRAM includes a pair of pull-up transistors 11 (PU1 and PU2), a pair of pull-down transistors 21 (PD1 and PD2) and first and second pass transistor AT1 and AT2. The first and second pass transistors AT1 and AT2, sometimes referred to as “access transistors”, have gates commonly connected to a word line (WL) node, and drains respectively connected to a bit line (BL) node and a bit line bar (BLB) node, respectively. Here, the BL and BLB nodes have complementary relationship.
A planar arrangement structure of the 6T CMOS SRAM cell of FIG. 1 is depicted in FIG. 2, which illustrates a typical layout of a CMOS SRAM cell. As can be deduced from FIG. 2, all of the transistors of the 6T CMOS SRAM of FIG. 1 are disposed in a common layer.
When the 6T CMOS SRAM cell as illustrated in FIG. 1 is constructed in a single common layer, the area occupied per cell is relatively increased, which serves to restrict high-density integration. Accordingly, in order increase device density, a technique of fabricating memory cells in a stacked-type arrangement has been developed. A particular example of a fabrication technique of stacking the memory cell transistors is disclosed in Korean Patent Application Nos. 2004-0002080 and 2004-0002088 filed by the same Applicant as the present disclosure.
By way of a first example for fabricating a single stacked-type memory cell, four N-type MOS transistors (pull-down and pass transistors) of the six MOS transistors constituting a static memory cell can be formed in a first semiconductor substrate layer while two P-type MOS transistors (pull-up transistors) can be formed in a second substrate layer, such as a channel silicon layer formed on gate electrodes of the N-type MOS transistors in an insulated fashion.
Continuing, FIG. 3 shows the CMOS SRAM cell of FIG. 1 located on the left side with an equivalent circuit diagram located to the right arrow line AW1 illustrating the case where the CMOS SRAM cell of FIG. 1 is formed as a three-layer stacked structure. The stacked cell illustrated on the right side of FIG. 3 has a structure in which first and second pull-down transistors PD1 and PD2 are disposed in a first layer, first and second pull-up transistors PU1 and PU2 are disposed in a second layer and first and second pass transistors AT1 and AT2 are disposed in a third layer. FIG. 4 illustrates the schematic cross-sectional structure of a stacked-type 6T CMOS SRAM cell of FIG. 3. FIGS. 5 and 6 illustrate the layout of a stacked-type 6T CMOS SRAM cell of FIG. 3.
Returning to FIG. 4, a semiconductor substrate 100 is shown having a number of P-wells 102 with a drain 104 and source 105 shown as embedded in a left-hand P-well. Agate insulating layer 108 is disposed over the left-hand P-well 102 separating a pull-down transistor gate (PDG) from P-well 102. Sidewall spacers 109 and 110 abut both sides of the PDG. Note that the PDG, a pull-up transistor gate (PUG), and pass transistor gate (ATG) are stacked in layers L1, L2, and L3 respectively. Conductive interconnect S2 serves to connect silicon layers CS1 and CS2, which are silicon layers formed by selective epitaxial growth interconnected, and conductive interconnect S1 serves to connect source 105 and layer CS1.
Continuing to the planar arrangement diagrams of FIGS. 5 and 6, it should be appreciated that it can be difficult to form a pattern for the ATG, which resides at the top of the stacked array of transistors.
Further, the stacked-type cell structure of FIG. 4 has a problem in that its bridge margin is weak with respect to a given cell node. Further, because driving performance of the pass transistor is lowered in proportion to the increase of the integration density of a semiconductor device, chip performance may suffer.
Thus, even in the case of semiconductor memories having stacked-type memory cells, a more preferable memory cell arrangement may be desirable.